As is known, programmable logic arrays basically comprise: an input latch, controlled by a first timing signal; a so-called "AND plane" effecting logic products of the input signals thereby generating the "product terms"; a so-called "OR plane" effecting logic sums of the product terms; and an output latch, controlled by a second timing signal. In dynamic logic arrays, logic operations and signal extraction take place in dependence upon a suitable control signal.
Nowadays such logic arrays are implemented in C-MOS technology, which is low-consuming and highly reliable.
For applications in which the operating rate of a dynamic logic array is important, precharge (or predischarge) schemes are used, wherein each output of the AND and OR planes is previously charged (discharged) by a transistor. This scheme requires the presence of a control or blocking circuit at the input of the AND and OR planes, which circuit sets the input signals to such a value that the output previously charged (discharged) cannot be significantly discharged (charged) owing to fluctuations of the input signals.
For high-speed precharge schemes, AND and OR functions are obtained by the use of NOR gates (hence the definition of NOR-NOR structure), and in these types of arrays the suitable value of the input signals is determined by combining input and enabling signals in NOR logic gates. This approach is described e.g. in Principles of C-MOS VLSI Design by N. H. Weste and K. Eshraghian, Addison-Wesley, 1985, Chapter 8, pages 368-379, and in The Design and Analysis of VLSI Circuits, by L. A. Glasser and D. N. Dobberpuhl, Addison-Wesley, 1985, Chapter 7, pages 383-388.
However, these systems have the disadvantage of decreasing the operation rate, since two transistors in series are always present, and of requiring a considerable area occupancy, depending on the number of transistors forming a NOR gate.